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1. general description the 74hc175-q100; 74hct175-q100 are quad posi tive edge-triggered d-type flip-flops with individual data inputs (dn) and both qn and q n outputs. the common clock (cp) and master reset (mr ) inputs load and reset all flip-flo ps simultaneously. the d-input that meets the set-up and hold time requirements on the low-to-high clock transition is stored in the flip-flop and appea rs at the q output. a low on mr causes the flip-flops and outputs to be reset low. the device is useful for applications where both the true and complement outputs are required and the clock and master reset are common to all storage elements. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? input levels: ? for 74hc175-q100: cmos level ? for 74hct175-q100: ttl level ? four edge-triggered d-type flip-flops ? asynchronous master reset ? complies with jedec standard no. 7a ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 74hc175-q100; 74hct175-q100 quad d-type flip-flop with re set; positive-edge trigger rev. 1 ? 19 may 2014 product data sheet
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 2 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74HC175D-Q100 ? 40 ? c to +125 ? c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74hct175d-q100 74hc175pw-q100 ? 40 ? c to +125 ? c tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 74hct175pw-q100 fig 1. logic symbol fig 2. iec logic symbol ddd ' ' ' ' 05 &3 4 4 4 4 4 4 4 4 ddd & ' 5 fig 3. logic diagram ddd 4 5' &3 05 4 )) ' ' ' ' ' 4 4 &3 4 5' 4 )) ' &3 4 5' 4 )) ' &3 4 5' 4 )) ' &3 4 4 4 4 4 4
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 3 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger 5. pinning information 5.1 pinning 5.2 pin description fig 4. pin configuration so16 fig 5. pin configuration tssop16 ddd 0 5 9 && 4 4 4 4 ' ' ' ' 4 4 4 4 *1' &3 +&4 +&74 ddd 9 && 4 4 ' ' 4 4 &3 4 4 ' ' 4 4 *1' 0 5 +&4 +&74 table 2. pin description symbol pin description mr 1 asynchronous master reset input (active low) q0 to q3 2, 7, 10, 15 flip-flop output q0 to q3 3, 6, 11, 14 complementary flip-flop output d0 to d3 4, 5, 12, 13 data input gnd 8 ground (0 v) cp 9 clock input (low-to-high edge-triggered) v cc 16 positive supply voltage
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 4 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger 6. functional description [1] h = high voltage level; h = high voltage level one set-up time prior to the low-to-high clock transition; l = low voltage level; l = low voltage level one set-up time prio r to the low-to-high clock transition; x = don?t care; ? = low-to-high clock transition. table 3. function table [1] operating modes inputs outputs mr cp dn qn qn reset (clear) l x x l h load ?1? h ? hhl load ?0? h ? llh fig 6. functional diagram ddd 4 5' &3 4 4 44 44 4 4 ' ' ' ' 05 4 )) ' &3 4 5' 4 )) ' &3 4 5' 4 )) ' &3 4 5' 4 )) ' &3
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 5 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger 7. limiting values [1] for so16 package: above 70 ? c the value of p tot derates linearly with 8 mw/k. for tssop16 packages: above 60 ? c the value of p tot derates linearly with 5.5 mw/k. 8. recommended operating conditions table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v) symbol parameter conditions min max unit v cc supply voltage ? 0.5 +7 v i ik input clamping current v i < ? 0.5 v or v i >v cc +0.5v - ? 20 ma i ok output clamping current v o < ? 0.5 v or v o >v cc +0.5v - ? 20 ma i o output current ? 0.5 v < v o < v cc +0.5v - ? 25 ma i cc supply current - 50 ma i gnd ground current ? 50 - ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation t amb = ? 40 ? c to +125 ?c [1] - 500 mw table 5. recommended operating conditions voltages are referenced to gnd (ground = 0 v) symbol parameter conditions 74hc175-q100 74hct175-q100 unit min typ max min typ max v cc supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 v v i input voltage 0 - v cc 0- v cc v v o output voltage 0 - v cc 0- v cc v t amb ambient temperature ? 40 - +125 ? 40 - +125 ?c ? t/ ? v input transition rise and fall rate v cc = 2.0 v - - 625 - - - ns/v v cc = 4.5 v - 1.67 139 - 1.67 139 ns/v v cc = 6.0 v--83---ns/v
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 6 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger 9. static characteristics table 6. static characteristics at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ max min max min max 74hc175-q100 v ih high-level input voltage v cc = 2.0 v 1.5 1.2 - 1.5 - 1.5 - v v cc = 4.5 v 3.15 2.4 - 3.15 - 3.15 - v v cc = 6.0 v 4.2 3.2 - 4.2 - 4.2 - v v il low-level input voltage v cc = 2.0 v - 0.8 0.5 - 0.5 - 0.5 v v cc = 4.5 v - 2.1 1.35 - 1.35 - 1.35 v v cc = 6.0 v - 2.8 1.8 - 1.8 - 1.8 v v oh high-level output voltage v i = v ih or v il i o = ? 20 ? a; v cc = 2.0 v 1.9 2.0 - 1.9 - 1.9 - v i o = ? 20 ? a; v cc = 4.5 v 4.4 4.5 - 4.4 - 4.4 - v i o = ? 20 ? a; v cc = 6.0 v 5.9 6.0 - 5.9 - 5.9 - v i o = ? 4.0 ma; v cc = 4.5 v 3.98 4.32 - 3.84 - 3.7 - v i o = ? 5.2 ma; v cc = 6.0 v 5.48 5.81 - 5.34 - 5.2 - v v ol low-level output voltage v i = v ih or v il i o = 20 ? a; v cc = 2.0 v - 0 0.1 - 0.1 - 0.1 v i o = 20 ? a; v cc = 4.5 v - 0 0.1 - 0.1 - 0.1 v i o = 20 ? a; v cc = 6.0 v - 0 0.1 - 0.1 - 0.1 v i o = 4.0 ma; v cc = 4.5 v - 0.15 0.26 - 0.33 - 0.4 v i o = 5.2 ma; v cc = 6.0 v - 0.16 0.26 - 0.33 - 0.4 v i i input leakage current v i = v cc or gnd; v cc =6.0v --? 0.1 - ? 1- ? 1 ? a i cc supply current v i = v cc or gnd; i o =0a; v cc =6.0v --8.0- 80 - 160 ? a c i input capacitance -3.5-- - - - pf 74hct175-q100 v ih high-level input voltage v cc = 4.5 v to 5.5 v 2.0 1.6 - 2.0 - 2.0 - v v il low-level input voltage v cc = 4.5 v to 5.5 v - 1.2 0.8 - 0.8 - 0.8 v v oh high-level output voltage v i = v ih or v il ; v cc = 4.5 v i o = ? 20 ? a 4.4 4.5 - 4.4 - 4.4 - v i o = ? 4.0 ma 3.98 4.32 - 3.84 - 3.7 - v v ol low-level output voltage v i = v ih or v il ; v cc = 4.5 v i o = 20 ? a; v cc = 4.5 v - 0 0.1 - 0.1 - 0.1 v i o = 5.2 ma; v cc = 5.5 v - 0.15 0.26 - 0.33 - 0.4 v i i input leakage current v i = v cc or gnd; v cc =5.5v --? 0.1 - ? 1- ? 1 ? a
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 7 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger 10. dynamic characteristics i cc supply current v i = v cc or gnd; i o =0a; v cc =5.5v --8.0- 80 - 160 ? a ? i cc additional supply current per input pin; v i =v cc ? 2.1 v; other inputs at v cc or gnd; v cc = 4.5 v to 5.5 v dn input - 40 144 - 180 - 196 ? a cp input - 60 216 - 270 - 294 ? a mr input - 100 360 - 450 - 490 ? a c i input capacitance -3.5-- - - - pf table 6. static characteristics ?continued at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ max min max min max table 7. dynamic characteristics gnd (ground = 0 v); c l = 50 pf unless otherwise specified; for test circuit, see figure 10 symbol parameter conditions 25 ?c ? 40 ?c to +85 ? c ? 40 ? c to +125 ?c unit min typ max min max min max 74hc175-q100 t pd propagation delay cp to qn, q n; see figure 7 [1] v cc = 2.0 v - 55 175 - 220 - 265 ns v cc = 4.5 v - 20 35 - 44 - 53 ns v cc =5v; c l =15pf-17---- - ns v cc = 6.0 v - 16 30 - 37 - 45 ns t phl high to low propagation delay mr to qn, q n; see figure 9 v cc = 2.0 v - 50 150 - 190 - 225 ns v cc = 4.5 v - 18 30 - 38 - 45 ns v cc =5v; c l =15pf-15---- - ns v cc = 6.0 v - 14 26 - 33 - 38 ns t t transition time qn output; see figure 7 [2] v cc = 2.0 v - 19 75 - 95 - 110 ns v cc = 4.5 v - 7 15 - 19 - 22 ns v cc = 6.0 v - 6 13 - 16 - 19 ns
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 8 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger t w pulse width cp input high or low; see figure 7 v cc = 2.0 v 80 22 - 100 - 120 - ns v cc = 4.5 v 16 8 - 20 - 24 - ns v cc = 6.0 v 14 6 - 17 - 20 - ns mr input low; see figure 9 v cc = 2.0 v 80 19 - 100 - 120 - ns v cc = 4.5 v 16 7 - 20 - 24 - ns v cc = 6.0 v 14 6 - 17 - 20 - ns t rec recovery time mr to cp; see figure 9 v cc = 2.0 v 5 ? 33 - 5 - 5 - ns v cc = 4.5 v 5 ? 12 - 5 - 5 - ns v cc = 6.0 v 5 ? 10 - 5 - 5 - ns t su set-up time dn to cp; see figure 7 v cc = 2.0 v 80 3 - 100 - 120 - ns v cc = 4.5 v 16 1 - 20 - 24 - ns v cc = 6.0 v 14 1 - 17 - 20 - ns t h hold time dn to cp; see figure 7 v cc = 2.0 v 25 2 - 30 - 40 - ns v cc = 4.5 v 5 0 - 6 - 8 - ns v cc = 6.0 v 4 0 - 5 - 7 - ns f max maximum frequency cp input; see figure 7 v cc = 2.0 v 6 25 - 4.8 - 4 - mhz v cc = 4.5 v 30 75 - 24 - 20 - mhz v cc =5v; c l =15pf - 83 - - - - - mhz v cc = 6.0 v 35 89 - 28 - 24 - mhz c pd power dissipation capacitance per package; v i =gndtov cc [3] -32---- - pf 74hct175-q100 t pd propagation delay cp to qn, q n; see figure 7 [1] v cc = 4.5 v - 19 33 - 41 - 50 ns v cc =5v; c l =15pf-16---- - ns table 7. dynamic characteristics ?continued gnd (ground = 0 v); c l = 50 pf unless otherwise specified; for test circuit, see figure 10 symbol parameter conditions 25 ?c ? 40 ?c to +85 ? c ? 40 ? c to +125 ?c unit min typ max min max min max
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 9 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger [1] t pd is the same as t phl and t plh . [2] t t is the same as t thl and t tlh . [3] c pd is used to determine the dynamic power dissipation (p d in ? w). p d = c pd ? v cc 2 ? f i + ?? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; ? (c l ? v cc 2 ? f o ) = sum of outputs; c l = output load capacitance in pf; v cc = supply voltage in v. t phl high to low propagation delay mr to qn; see figure 9 v cc = 4.5 v - 22 38 - 48 - 57 ns v cc =5v; c l =15pf-19---- - ns mr to q n; see figure 9 v cc = 4.5 v - 19 35 - 44 - 53 ns v cc =5v; c l =15pf-16---- - ns t t transition time qn output; see figure 7 [2] v cc = 4.5 v - 7 15 - 19 - 22 ns t w pulse width cp input; see figure 7 v cc = 4.5 v 20 12 - 25 - 30 - ns mr input low; see figure 9 v cc = 4.5 v 20 11 - 25 - 30 - ns t rec recovery time mr to cp; see figure 9 v cc = 4.5 v 5 ? 10 - 5 - 5 - ns t su set-up time dn to cp; see figure 7 v cc = 4.5 v 16 5 - 20 - 24 - ns t h hold time dn to cp; see figure 7 v cc = 4.5 v 5 0 - 5 - 5 - ns f max maximum frequency cp input; see figure 7 v cc = 4.5 v 25 49 - 20 - 17 - mhz v cc =5v; c l =15pf - 54 - - - - - mhz c pd power dissipation capacitance per package; v i =gndtov cc ? 1.5 v [3] -34---- - pf table 7. dynamic characteristics ?continued gnd (ground = 0 v); c l = 50 pf unless otherwise specified; for test circuit, see figure 10 symbol parameter conditions 25 ?c ? 40 ?c to +85 ? c ? 40 ? c to +125 ?c unit min typ max min max min max
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 10 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger 11. waveforms measurement points are given in table 8 . fig 7. input to output propagation delay, output transition time, clock input pulse width and maximum frequency ddd w : w 3+/ w 3+/ w 7/+ w 7+/ w 7/+ 9 0 9 0 i pd[ w 3/+ w 7+/ w 3/+ 9 0 & 3lqsxw 4qrxwsxw 4qrxwsxw *1' 9 , 9 2/ 9 2+ 9 2/ 9 2+ measurement points are given in table 8 . fig 8. data set-up and hold times for data input ddd 9 0 & 3lqsxw 'qlqsxw 4qrxwsxw 4qrxwsxw 9 0 9 0 9 0 w vx w vx w k w k *1' 9 , *1' 9 , 9 2/ 9 2+ 9 2/ 9 2+
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 11 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger measurement points are given in table 8 . fig 9. master reset to output propagation delays, master reset pulse width and mast er reset to clock recovery time 4qrxwsxw ddd 9 0 w : w uhp 9 0 9 0 9 0 w 3+/ & 3lqsxw 0 5lqsxw 4qrxwsxw w 3/+ *1' 9 , *1' 9 , 9 2/ 9 2+ 9 2/ 9 2+ table 8. measurement points type input output v i v m v m 74hc175-q100 v cc 0.5v cc 0.5v cc 74hct175-q100 3 v 1.3 v 1.3 v
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 12 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger test data is given in table 9 . definitions for test circuit: r t = termination resistance should be equal to output impedance z o of the pulse generator. c l = load capacitance including jig and probe capacitance. r l = load resistance. fig 10. test circuit for measuring switching times 001aah768 t w t w t r t r t f v m v i negative pulse gnd v i positive pulse gnd 10 % 90 % 90 % 10 % v m v m v m t f v cc dut r t v i v o c l g table 9. test data type input load test v i t r , t f c l r l 74hc175-q100 v cc 6ns 15pf, 50 pf 1k ? t plh , t phl 74hct175-q100 3 v 6 ns 15 pf, 50 pf 1 k ? t plh , t phl
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 13 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger 12. package outline fig 11. package outline sot109-1 (so16) x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 14 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger fig 12. package outline sot403-1 (tssop16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 15 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger 13. abbreviations 14. revision history table 10. abbreviations acronym description cmos complementary metal-oxide semiconductor dut device under test esd electrostatic discharge hbm human body model mil military mm machine model ttl transistor-transistor logic table 11. revision history document id release date data sheet status change notice supersedes 74hc_hct175_q100 v.1 20140519 product data sheet - -
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 16 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74hc_hct175_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 1 ? 19 may 2014 17 of 18 nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74hc175-q100; 74hct175-q100 quad d-type flip-flop with reset; positive-edge trigger ? nxp semiconductors n.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 19 may 2014 document identifier: 74hc_hct175_q100 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 functional description . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 recommended operating conditions. . . . . . . . 5 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 16 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 16 contact information. . . . . . . . . . . . . . . . . . . . . 17 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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